1. Field of the Invention
The present invention relates to a trench isolation and a method of forming thereof, and more particularly to a narrow-channel effect free transistor by employing a conductive shield embedded in the trench isolation.
2. Description of the Related Art
Integrated circuit fabrication usually requires that the individual active and passive circuit elements be electrically isolated form each other in the common semiconductor chip so that desired circuit connections can be made by patterned surface metallization with which the isolated circuit elements are in contact. Many diverse techniques have been proposed, ranging from junction isolation to dielectric isolation and to combinations thereof, to accomplish the desired isolation.
As device dimensions get smaller, and device density increases, it becomes more and more difficult to build an efficient and reliable isolation process to separate active devices. The limits of the standard LOCOS process have motivated the search for and the development of new isolation schemes, and trench isolation is a promising candidate as it uses a fully recessed oxide, has no bird's beaks, is fully planar, and does not suffer from the field oxide thinning effect.
As the integration level of semiconductor memory devices increases, the integration level is progressing to a DRAM device having a size of a Gbit or more. Since components of a Gbit unit device are scaled down to less than 0.20 micrometers(i.e., 0.1 micrometers of minimum feature size), the likelihood that problems associated with channel width of the transistor may occur increases greatly.
Since DRAM cell transistor requires a threshold voltage of at least 1V or more independent of the DRAM density and operation voltage, the channel doping density must increase significantly in order to offset decrease in the threshold voltage caused by the scaling down of transistor dimension. FIG. 1 schematically shows the relationship between the gate length, doping density and the degree of memory device density. As can be seen in FIG. 1, if the channel length of the transistor is about 0.1 micrometers, it is required that the substrate doping density be at least 2.times.10.sup.18 /cm.sup.-3 in order to adjust threshold voltage of the transistor at a level of about 1V. If the channel length decreases furthermore, the substrate doping density must be increased. Such increase in the substrate doping density causes undesirable side-effects as follows.
The cell transistor suffers form increased junction leakage current due to high substrate doping, and serous threshold voltage variation caused by active width CD variation and enhanced narrow-channel effect. The breakdown voltage significantly decreases due to a tunnelling phenomenon and thereby increasing leakage current of a storage node. High substrate doping density increases junction capacitance and thereby increasing parasitic capacitance and increases depletion capacitance.
Even more, when the isolation pitch is scaled down to less than 0.2 micrometers, serous threshold voltage fluctuation will be induced by the neighbouring drain E-field penetration effect. Namely, when the shallow trench isolation space is scaled down to less than 0.1 micrometers, the drain/source E-field penetration into the sidewall depletion region from the neighbouring cell transistors will increase. The drain/source E-field penetration will result in the barrier lowering near the center of the active cell transistor channel, and the threshold voltage will fluctuate depending on the junction voltages of the neighbouring cell transistors. So, threshold voltage of the DRAM cell transistors becomes difficult to be scaled down as the operation voltage decreases owing to increased threshold voltage variation. For the low voltage operation DRAMs, unscalable threshold voltage will seriously impact the DRAM speed performance of t.sub.RAC and t.sub.RCD due to degraded saturation current. Therefore, in order to satisfy the tight electrical requirement for low voltage/power and high speed operation, threshold voltage should be scaled down while minimizing its variation caused by active width DC variation and narrow channel effect.